1. Field of the Invention
This invention relates to computer systems and more particularly to power management architectures employed within computer systems.
2. Description of the Relevant Art
An ongoing developmental goal of manufacturers has been to reduce the power consumption of computer systems. Reducing power consumption typically reduces heat generation of the system, thereby increasing reliability and decreasing cost. In addition, power reduction has been particularly important in maximizing the operating life of battery-powered portable computer systems.
Various techniques have been devised for reducing the power consumption of computer systems. These techniques include increasing the integration of circuitry and incorporation of improved circuitry and power management units (PMUs). One specific power reduction technique involves the capability of stopping clock signals that drive inactive circuit portions. A system employing such a technique typically includes a power management unit that detects or predicts inactive circuit portions and accordingly stops the clock signals associated with the inactive circuit portions. By turning off "unused" clock signals that drive inactive circuit portions, overall power consumption of the system is decreased. A similar technique involves the capability of reducing the frequency of clock signals that drive circuit portions during operating modes which are not time critical, and another technique involves the capability of removing power from inactive circuit portions.
Power managed computer systems that employ the above-described power reduction techniques typically monitor various activities at the point of use or by snooping centralized buses. For example, an activity monitor of a power management unit may be connected directly to various control lines associated with the microprocessor and peripheral devices to determine whether certain activities are occurring. Depending upon the detected activities, the power management unit may responsively power down selected circuit portions, reduce the frequencies of selected clock signals and/or completely stop selected clock signals.
In recent years, integrated processors have been developed to replace previously discrete microprocessors and associated peripheral devices within computer systems. An integrated processor is an integrated circuit that performs the functions of both a microprocessor and various peripheral devices such as, for example, a memory controller, a DMA controller, a timer, and a bus interface unit, among other things. The introduction of integrated processors has allowed for decreases in the overall cost, size, and weight of computer systems, and has in many cases accommodated improved performance characteristics of the computer systems.
A problem encountered in the design of computer systems that incorporate integrated processors is that many points of monitoring are no longer available to an external power management unit. That is, since the CPU core and various peripheral devices are contained on a common integrated circuit chip, internal connections between the CPU core and the peripheral devices may not be accessible externally. Thus, certain system activities may be undetectable in real-time. Although external package pins could be provided on the integrated processor to provide external access directly to the selected internal points of monitoring, such dedicated pins would result in a significant increase in the overall pin count of the integrated processor and would further require that the die size of the integrated processor be increased to accommodate the additional bond wire pads. As a result, a significant cost would be added to the cost of the integrated processor.
On the other hand, rather than providing an external power management unit, a power management unit could be incorporated as an integral part of the integrated processor itself. However, this would limit the flexibility available to the system designer in implementing different power management designs using the same processor.
A further problem associated with computer systems including those that incorporate integrated processors involves the determination of how the power management unit should treat each detected activity. Although a variety of systems have been proposed in which the power management unit causes the frequencies of selected clock signals to be raised if certain system activities are detected and to be lowered if the system activities are not detected, such systems typically do not treat the detected activities differently. As a result, the efficiency of these systems may be somewhat limited since many detected activities have different associated impacts upon power consumption than others.